Form there, the area saving size trend cascades. In a IC design, a NAND gate uses less area then NOR gate because of characteristic properties of a NMOS and PMOS. For the sake of simplicity designs based on SR/SnRn latches will be be refereed to as "Classical" and "Modern" for designs using mentioned D-latch/S-cell patents. An 8-transitor D-latch was patent was filed US3641511 A. The modern master/slave components of a D-flip-flop can use two 5-transistor latches Patents WO1984003806 A1 and US4484087 A both filed on Mar 23, 1984. Modern pos/neg-edge DFFs often have equal total area, therefore the positive-edge trend is now legacy practice.Īrea saving came form "Classical" D-flip-flop designs. A cost saving measure for production by increase the number of chip per wafer. Best guess: the positive-edge trend is a byproduct of designs trying to use a little area/parts as possible before the 1970's.
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